Journal of VLSI Circuits and Systems

An Efficient Error Resilient Ternary Content Addressable Memory Architecture

Sirisha Mallaiah — 2026-02-26

High-speed memories like TCAM (Ternary Content Addressable Memory) are widely employed in highthroughput search applications like network routers. Using ASIC (Application-Specific Integrated Circuits) to construct TCAM memories allows for a higher search rate at the expense of increased power and resource requirements. However, safeguarding the TCAM from soft errors while maintaining good search speed and minimizing critical path time is a difficult task. In this paper, we present a TCAM architecture with a multipumping technique that incorporates the correction of multiple bits using the Hamming code. Different sizes, such as 4x4, 16x8 and 32x16, of the proposed TCAM architecture are simulated and implemented in 45nm technology. The proposed work evaluates
the TCAM in comparison to the Look-Up Table (LUT) based on a priority encoder in TCAM architecture, Two-Dimensional (2D) parity, Three-Dimensional (3D) parity, and Hamming code-based error correction methods with a multiplexer block in TCAM architecture. The results demonstrate that the suggested TCAM has a lesser delay compared to the LUT-based and higher error
correction capability, including the parity bits.

Auto-PPA: An Adaptive Deep RL Agent for VLSI Physical Design Optimization

Hussain Ali Mutar — 2026-02-26

The physical design phase of Very-Large-Scale-Integration (VLSI) is notoriously difficult since it must strike a balance between PPA, power, and performance. Computationally costly design cycles and less-than-ideal Pareto fronts are common challenges of using traditional optimization methods to tackle these metrics in order. As part of physical design, this study suggests a new reinforcement learning (RL) framework that can optimize all three PPA measures in real time. In the proposed method, commercial electronic design automation (EDA) tools were used in conjunction with a deep deterministic policy gradient (DDPG) agent to make routing and placement decisions incrementally. Guided by a customized reward function that dynamically balances PPA trade-offs based on design stage priorities, the agent operates on a continuous action space that represents geometric coordinates and constraint modifications. While conventional sequential optimization methodologies reduce optimization runtime by about 35%, the proposed RL agent improves the power-performance product by 18.7% and the area reduction by 12.3%, according to simulation results on the ISPD 2015 benchmark suite. An innovative approach to optimize intelligent, adaptable physical designs that successfully traverse the high-dimensional PPA trade-off space is presented by the suggested framework.

Resource-Constrained VLSI Architecture for Wearable Health Monitoring: Integrating On-Chip Data Compression with CNN-Based Fall and Arrhythmia Detection

Akmaljon Mamatov — 2026-03-28

Wearable biomedical devices need to achieve two opposing goals, which require them to process data instantaneously while consuming minimal power to maintain their battery power throughout extended periods. The standard processing system, which most systems use, depends on cloud computing, but this method creates security vulnerabilities and time delays for users. The research introduces a new low-power AI-based Very-Large-Scale Integration (VLSI) design that scientists created specifically for use in wearable health monitoring devices that need to detect falls and identify cardiac arrhythmias. The primary development of this project is the creation of a hardware-based preprocessing compression unit that employs delta-encoding to reduce data duplication prior to the neural network performing its computations. Our system uses a lightweight convolutional neural network accelerator, which processes accelerometer and ECG data using mixed-precision arithmetic at the edge. The architectural design achieves fall detection accuracy of 95.4% while requiring only 24.8 μJ of energy for each inference, according to simulation results obtained through 65 nm CMOS technology testing. The system provides the next generation of remote patient monitoring systems with essential energy-efficient design elements that produce a 28% better energy output when compared to existing baseline systems.

Design and Analysis of 4-bit Reconfigurable Johnson Counter using 18nm finFET

M. Bala Murali Krishna — 2026-04-25

The counter is used widely as an important component in measurement systems. Hybrid logic has one prominent advantage in the construction of counter circuits because it requires a minimal number of transistors and demands low power. This work is a reconfigurable 4-bits Johnson counter. When the mode is set to one, the counter is used for counting. In this configuration, the flip - flops are initialized after four clock cycles provided that the reset (RST) signal is low. If RST is high then the counter performs its normal counting operation. When mode is off the counter is changed by resetting the last bit of the count vector to its initial value. The flip flip is the basic component of the proposed counter. To realize a low power, high speed and low complexity counter, we implemented a mixed logic flip flop. This flip flop is realized using 18 transistors, that is 9 PFETs and 9 NFETs. It is just made up of complementary logic and pass gate transistor and has succeeded in terms of increase speed, power and circuit complexity. The obtained results were achieved using Cadence Virtuoso at finFET technology node 18nm. Experiments were done in different process corners, with supply voltages ranging from 0.7V to 1.0V, and temperatures varying from -25 ⁰C to 75 ⁰C. Based on the results, the proposed counter shows tremendous stability.

Design and Verification of FPGA-based Range Processing, Peak Detection and Doppler Processing for FMCW-RADAR

Suganthi K — 2026-04-28

Modern RADAR systems produce a large amount of data that must be processed quickly and accurately for reliable target detection. Software-based processing methods often struggle to meet real-time requirements due to high latency and computational overhead. This work presents a fully streaming, Field Programmable Gate Array (FPGA)-based peak detection architecture tightly integrated within the Range–Doppler processing pipeline. Continuous magnitude data from the Range and Doppler Fast Fourier Transform (FFT) stages is transferred using an Advanced eXtensible Interface (AXI)-Stream interface, enabling seamless integration between Xilinx FFT IP cores and a custom peak detection accelerator without intermediate memory storage. Unlike conventional radar systems that construct a two-dimensional Range–Doppler map followed by explicit scanning, the proposed approach performs detection on a linearized data stream. This eliminates the need for complex 2D search logic, reduces control overhead, and enables low-latency,
real-time operation suitable for practical radar deployments. Additionally, index-aware detection logic propagates range and Doppler indices alongside magnitude data, enabling direct extraction of target coordinates without post-processing. The modular AXI-Stream architecture ensures reusability, timing-closed operation, and reduced FPGA resource utilization compared to reference designs. The proposed system emphasizes FPGA-focused architectural optimization rather than algorithm-level modification, distinguishing it from
prior software-oriented or hybrid detection approaches. The complete processing chain achieves an end-to-end latency of approximately 1.1 ms for a full frame comprising 64 chirps, while sustaining a continuous input data rate exceeding 200 MSamples/s. The design was synthesized and simulated using the Xilinx Vivado design tool and implemented on a Zynq-7000-based ZC702 evaluation board, demonstrating efficient FPGA resource utilization of approximately 35% LUTs, 28% flip-flops, 42% BRAM, and 6 DSP slices. Simulation results confirm correct FFT operation, reliable buffering, and accurate peak detection across varying signal-to-noise ratios. The proposed architecture offers low latency, high throughput, and efficient hardware utilization, making it well-suited for practical real-time radar signal processing applications. Overall, the proposed FPGA-based solution demonstrates low latency, efficient resource usage, and reliable real-time performance, making it suitable for practical Frequency Modulated Continuous Wave (FMCW)-RADAR signal processing applications.

Design of 45nm CMOS Front-End LNA for RF Receiver

Vijaya Sri Domadula — 2026-05-21

This study explains the design and analysis of a CMOS RF receiver front-end low-noise amplifier (LNA) at 45 nm, intended for wireless communication at approximately 3.4 GHz. This proposed architecture uses a cascaded inductive-degeneration topology, enabling balanced optimization of gain, noise figure, impedance matching, and power consumption. This contrasts with traditional single-stage CMOS RF front-end LNAs, which amplify through
a single stage, creating load and, worse still, reverse isolation. A cascaded configuration allocates amplification between stages, eliminates loading effects, and enhances reverse isolation, but at the expense of a lower noise contribution. The networks of input and output matching are designed to ensure that return losses do not exceed the −10 dB threshold, thereby guaranteeing stable operation within the industry target frequency range. Simulations show a forward gain (S21) of 32.6 dB, a noise figure of 0.96 dB, an input return loss of −11.6 dB, and a power consumption of 9.8 mW with a 1 V supply. A detailed comparative analysis of architectural and performance variations between two closely related CMOS RF receiver front-end designs is presented, demonstrating improved gain-to-power efficiency due to topology refinement. Additionally, process-voltage-temperature (PVT) testing is conducted to assess robustness under realistic operating conditions, ensuring consistent RF performance across process corners and environments. The findings show that the design under consideration offers an integration-based RF front-end suitable for broadband receiver applications.

Full-Swing Gate Diffusion Input Based 32-Bit Arithmetic and Logic Unit: Design, Implementation, and Comparative Analysis

Rekha P — 2026-06-15

This paper presents the design and implementation of a 32-bit arithmetic logic unit (ALU) using the full-swing gate diffusion input (FS-GDI) technique for low-power and area-efficient digital systems. The ALU performs various arithmetic, logical, and shift operations, and
adopts a modular approach by building 1-bit FS-GDI cell and scaling to 32 bits with a Brent– Kung parallel prefix adder in the arithmetic path to balance speed and hardware complexity. Comparative implementations of the same ALU were produced in CMOS, gate diffusion input (GDI), modified-gate diffusion input (M-GDI), and FS-GDI using 45nm technology for a fair assessment. Simulation results show that the FS-GDI design achieves large reductions in power and area: a 98.42% reduction in static power, 47.64% reduction in dynamic power, 74.76% reduction in average power, 62.79% reduction in transistor count, and 70.91% reduction in power delay product (PDP), with only a minor 14.7% increase in propagation delay versus a CMOS baseline, with overall PDP improvement and acceptable timing tradeoffs. The paper also analyzes alternate adder choices, and motivates the choice of Brent–Kung for the final design. Results validate that FS-GDI provides an effective trade-off for lowpower, full-swing logic in high bit-width ALUs.

A Hardware-Efficient LUT Optimized Fault-Tolerant Reversible 64-bit Arithmetic Processor with Self-Error Correction

Veeresh K — 2026-06-19

The increasing demand for reliable and energy-efficient computing in safety and critical applications such as aerospace systems, embedded control systems and intelligent computing platforms requires processor architecture that simultaneously achieves low power consumption, high performance and robust fault tolerance. From this environment, transient and permanent errors are caused by radiation effects, voltage fluctuation, noise and timing violation, and it can significantly degrade computational accuracy and system reliability, especially in wide data path arithmetic operations. This research addresses the problem of designing an energy-efficient and fault-resilient arithmetic processor that maintains reliable operations without incurring excessive hardware overhead. To meet this objective, a self-error correction of fault tolerant 64-bit arithmetic processor architecture is proposed with reversible logic, in which parity-based error detection and Hamming code-based error correction are systematically integrated across the processor data path. The proposed design employs reversible majority-based arithmetic units, which extends error protection beyond the arithmetic core operations to include registers, branch related arithmetic and logic operation and memory interface, and ensures functional completeness for general- purpose computation. This work proposed the novelty architecture lies in the unified integration of reversible logic with a processor with wide forward error correction, enabling reliable single-bit error correction while preserving low power characteristics and reducing unnecessary logic activity. The complete design is developed using Verilog HDL and synthesized on an Artix-7 FPGA using the Xilinx Vivado design suite. The experimental results demonstrate that the proposed architecture achieves a notable reduction in LUT utilization and power consumption and significantly improves fault tolerance.

Low-Power FPGA Implementation of an 8-Bit Quantized MLP Neural Network for Real-Time Vehicular Prediction

Raneen Alaa Ogla — 2026-07-01

Real-time vehicular monitoring systems increasingly rely on predictive analytics to improve transportation safety and efficiency. However, software-based ML on microcontrollers faces limitations such as high latency and power consumption. This work proposes a low-power hardware implementation of a quantized multi-layer perceptron for vehicle prediction on an FPGA for vehicle monitoring.

The proposed design combines GPS data collection, preprocessing, neural network prediction, and GSM transmission on a single VHDL-based embedded system. An 8-bit fixed-point quantization and pipelined MADD network are used to achieve high parallelization on an FPGA. Temporal GPS data analysis is performed to predict short-term vehicle trajectory and driving behavior.

The proposed design has a latency of ~2-3 ms and a power consumption of ~640 mW on an Artix-7 FPGA. The logic and DSP resources are efficiently utilized for this implementation. The proposed design achieves a position error of less than three meters for a three-second horizon for vehicle trajectory prediction.

Hardware acceleration for neural network inference on an FPGA can be a scalable and power-efficient solution for real-time vehicle monitoring and prediction.

A Hardware-Efficient Pipelined Parallel Architecture for Low-Power Trivium Cipher in Internet of Things and Embedded Applications

Praveen Kumar M S — 2026-07-02

Embedded devices and Internet of Things (IoT) have increased the need for lightweight cryptographic techniques that offer high security, are energy-efficient, and perform well. Trivium is a stream cipher that is a part of eSTREAM and can be easily implemented in
hardware, but most implementations have difficulties in achieving standard measures of efficiency. In this paper, we have suggested a hardware-efficient Trivium architecture that utilizes pipelining on top of parallelism to generate keystreams for each stage of the
Trivium pipeline. Clock gating, resource sharing, and bit-slice designs have been employed to minimize power consumption in the architecture and also the area consumed. A Xilinx Artix-7 FPGA implementation of the architecture has reached throughput up to 192Mb/s; it is 36 percent power efficient and 121 area efficient than previous state-of-the-art work. The architecture suggested offers a scalable design specific to the resource-constrained IoT and embedded applications that are cost-efficient and have low energy needs.

Hybrid CNN–VLSI Background Subtraction Framework for Intelligent Edge Vision

Veerabhadraswamy K.M — 2026-07-13

Background subtraction is a critical component of intelligent vision systems such as realtime (RT) surveillance, autonomous vehicles, and smart infrastructure at the network edge. Traditional methods based on deep learning are extremely accurate but highly computationally intensive (high energy) making them impractical for deployment on resource-constrained edge devices. Traditional hardware methods for background subtraction have very simple implementation requirements and typically low power consumption but may not be suitable in very fast-changing environments. This paper describes the development of a hybrid CNN–VLSI background subtraction framework that combines together lightweight convolutional neural network designs with high energy–efficient VLSI background subtraction hardware for accurate, RT extraction of foreground images from edge platforms. The framework consists of a CNN-based adaptive background modelling unit for scene understanding. It also has a custom VLSI accelerator that performs pixel-level background subtraction, thresholding, and morphological operations on the output from the CNN unit. Assessment of the performance of this approach using test benchmark datasets showed that it achieved comparable accuracy to traditional approaches while providing reduced latency and reduced power consumption of more than six times better than traditional software-only based CNN background subtraction approaches. This work represents a viable solution for developing energy-efficient intelligent edge vision systems that is scalable and suitable for use in RT applications.

A Differential CMOS Active Mixer with Enhanced Conversion Gain for Portable Ground Penetrating Radar Receivers

Asharani M — 2026-07-13

This paper presents the design, layout implementation, and performance evaluation of a differential CMOS active mixer intended for portable ground penetrating radar (GPR) receiver front-end applications. The proposed mixer employs a differential architecture
consisting of an RF transconductance stage and a local oscillator (LO) switching stage to achieve efficient frequency conversion from RF to IF while maintaining low noise and adequate linearity. The circuit schematic is designed and simulated, followed by physical layout implementation using Cadence Virtuoso, where careful layout techniques such as symmetry and device matching are applied to improve performance and minimize parasitic effects. The layout is verified using design rule check (DRC) and layout versus schematic
(LVS) procedures to ensure design correctness and fabrication compatibility. Simulation results show that the mixer achieves a maximum conversion gain (S21) of 15.48 dB at 2.4GHz. Noise analysis indicates a noise figure of approximately 5.31 dB at the same frequency, demonstrating good noise performance for radar receiver applications. Linearity characteristics obtained from harmonic balance analysis show an input-referred 1 dB compression point of −9.56 dBm, indicating acceptable large-signal handling capability. The combination of high conversion gain, moderate noise figure, and verified layout implementation confirms that the proposed CMOS mixer is suitable for integration in compact and energy-efficient GPR front-end systems.

Detection and Analysis of Hardware Trojans in Digital Adder Architectures

Allagadda Seetharamaraju — 2026-07-29

Globalization of integrated circuit (IC) manufacturing has made the implementation of malicious modifications, otherwise known as hardware Trojans, a physical challenge to the integrity and security of arithmetic units. Adders, which form a key element of most digital subsystems, are particularly sensitive to such attacks. This paper explores the impact of information-leakage and function-destructive Trojans inserted into the framework of a 13-transistor hybrid full-adder architecture. The Trojans make use of an AND-based trigger coupled with an XOR-based payload; their impact is measured through complete simulations run in a 45nm CMOS process under a 1V supply voltage. It has been found that, upon insertion of the Trojan, large degradations occur in key performance metrics such as power dissipation, which increases by 0.79 μW to 2.04 μW, and propagation delay, which can increase by 0.02ns to 49.72ns. Trojan-infected adders have a much higher power consumption than the nominal design and can consume multiple times more power than the nominal design, depending upon operating conditions. Thermal analysis shows increased power consumption, with the highest power consumption being 4.85mW at 75 °C. The same tendencies can be found in both slow slow (SS) and fast fast (FF) configurations, giving an impression of the sensitive nature of Trojan-affected adders to process voltage temperature (PVT) variations. These results provide a thorough assessment of the vulnerability of hybrid adders to hardware Trojans and highlight the need to strengthen the detection and countermeasures in the design of arithmetic circuits.

10-bit 45.5-Ms/s Asynchronous Successive Approximation ADC with a Differential CDAC Switching Circuit in 45 nm CMOS

Alwin Thomas — 2026-07-29

A 1.2 V 10-bit asynchronous successive approximation register (SAR) constructed with CMOS technology and an analog-to-digital converter (ADC) are proposed here in this study. An internal clock generator, a capacitive digital-to-analog converter, a sample-and-hold switch, SAR Logic, and a dynamic comparator form the asynchronous SAR ADC system. A maximum of ENOB for a sampling frequency of 45.5 MHz is 9.5 bits, the signal-to-noise ratio of which is 58.9 dB, while the overall power consumption is 167.16 μW, calculated based on a 64-point FFT of the Successive Approximation ADC’s output and input signals of 1.2 V differentially. The figure-of-merit obtained by Walden’s calculation is 14.5 fJ/step. Applications where low power, medium resolution, and medium speed are primarily required, for example, computing-in-memory cores for artificial intelligence and sensors used for biomedical applications, can employ this SAR ADC system.

Temperature-Dependent Electrical Behavior of SiGe-FinFETs with Different Gate Lengths

Yousif Atalla — 2026-07-29

The research investigated the influence of temperature on the sensitivity of MOS and Fin Field-Effect transistor (FinFET) transistors featuring an inhomogeneous composition of 50% silicon and Germanium. Using gate lengths (Lg = 10, 20, and 30 nm) and various thermal conditions, the study analyzed the current–voltage (I–V) characteristics. FinFET transistors exhibit peak thermal sensitivity at 0–1 V, and further reducing channel length increases thermal sensitivity, particularly in the 10–20 nm range. The optimal channel length was determined to be about 10 nm for excellent thermal performance. This research provides detailed temperature analysis that serves as a baseline for developing FinFET transistors with high thermal efficiency and stability across a variety of applications.