Journal of VLSI Circuits and Systems

An Efficient Error Resilient Ternary Content Addressable Memory Architecture

2025-09-19T11:18:11+02:00

High-speed memories like TCAM (Ternary Content Addressable Memory) are widely employed in highthroughput search applications like network routers. Using ASIC (Application-Specific Integrated Circuits) to construct TCAM memories allows for a higher search rate at the expense of increased power and resource requirements. However, safeguarding the TCAM from soft errors while maintaining good search speed and minimizing critical path time is a difficult task. In this paper, we present a TCAM architecture with a multipumping technique that incorporates the correction of multiple bits using the Hamming code. Different sizes, such as 4x4, 16x8 and 32x16, of the proposed TCAM architecture are simulated and implemented in 45nm technology. The proposed work evaluates
the TCAM in comparison to the Look-Up Table (LUT) based on a priority encoder in TCAM architecture, Two-Dimensional (2D) parity, Three-Dimensional (3D) parity, and Hamming code-based error correction methods with a multiplexer block in TCAM architecture. The results demonstrate that the suggested TCAM has a lesser delay compared to the LUT-based and higher error
correction capability, including the parity bits.

Auto-PPA: An Adaptive Deep RL Agent for VLSI Physical Design Optimization

2026-01-24T00:46:12+01:00

The physical design phase of Very-Large-Scale-Integration (VLSI) is notoriously difficult since it must strike a balance between PPA, power, and performance. Computationally costly design cycles and less-than-ideal Pareto fronts are common challenges of using traditional optimization methods to tackle these metrics in order. As part of physical design, this study suggests a new reinforcement learning (RL) framework that can optimize all three PPA measures in real time. In the proposed method, commercial electronic design automation (EDA) tools were used in conjunction with a deep deterministic policy gradient (DDPG) agent to make routing and placement decisions incrementally. Guided by a customized reward function that dynamically balances PPA trade-offs based on design stage priorities, the agent operates on a continuous action space that represents geometric coordinates and constraint modifications. While conventional sequential optimization methodologies reduce optimization runtime by about 35%, the proposed RL agent improves the power-performance product by 18.7% and the area reduction by 12.3%, according to simulation results on the ISPD 2015 benchmark suite. An innovative approach to optimize intelligent, adaptable physical designs that successfully traverse the high-dimensional PPA trade-off space is presented by the suggested framework.

Resource-Constrained VLSI Architecture for Wearable Health Monitoring: Integrating On-Chip Data Compression with CNN-Based Fall and Arrhythmia Detection

2026-01-31T08:11:45+01:00

Wearable biomedical devices need to achieve two opposing goals, which require them to process data instantaneously while consuming minimal power to maintain their battery power throughout extended periods. The standard processing system, which most systems use, depends on cloud computing, but this method creates security vulnerabilities and time delays for users. The research introduces a new low-power AI-based Very-Large-Scale Integration (VLSI) design that scientists created specifically for use in wearable health monitoring devices that need to detect falls and identify cardiac arrhythmias. The primary development of this project is the creation of a hardware-based preprocessing compression unit that employs delta-encoding to reduce data duplication prior to the neural network performing its computations. Our system uses a lightweight convolutional neural network accelerator, which processes accelerometer and ECG data using mixed-precision arithmetic at the edge. The architectural design achieves fall detection accuracy of 95.4% while requiring only 24.8 μJ of energy for each inference, according to simulation results obtained through 65 nm CMOS technology testing. The system provides the next generation of remote patient monitoring systems with essential energy-efficient design elements that produce a 28% better energy output when compared to existing baseline systems.

Design and Analysis of 4-bit Reconfigurable Johnson Counter using 18nm finFET

2026-01-31T08:16:58+01:00

The counter is used widely as an important component in measurement systems. Hybrid logic has one prominent advantage in the construction of counter circuits because it requires a minimal number of transistors and demands low power. This work is a reconfigurable 4-bits Johnson counter. When the mode is set to one, the counter is used for counting. In this configuration, the flip - flops are initialized after four clock cycles provided that the reset (RST) signal is low. If RST is high then the counter performs its normal counting operation. When mode is off the counter is changed by resetting the last bit of the count vector to its initial value. The flip flip is the basic component of the proposed counter. To realize a low power, high speed and low complexity counter, we implemented a mixed logic flip flop. This flip flop is realized using 18 transistors, that is 9 PFETs and 9 NFETs. It is just made up of complementary logic and pass gate transistor and has succeeded in terms of increase speed, power and circuit complexity. The obtained results were achieved using Cadence Virtuoso at finFET technology node 18nm. Experiments were done in different process corners, with supply voltages ranging from 0.7V to 1.0V, and temperatures varying from -25 ⁰C to 75 ⁰C. Based on the results, the proposed counter shows tremendous stability.

Design and Verification of FPGA-based Range Processing, Peak Detection and Doppler Processing for FMCW-RADAR

2026-02-13T13:24:37+01:00

Modern RADAR systems produce a large amount of data that must be processed quickly and accurately for reliable target detection. Software-based processing methods often struggle to meet real-time requirements due to high latency and computational overhead. This work presents a fully streaming, Field Programmable Gate Array (FPGA)-based peak detection architecture tightly integrated within the Range–Doppler processing pipeline. Continuous magnitude data from the Range and Doppler Fast Fourier Transform (FFT) stages is transferred using an Advanced eXtensible Interface (AXI)-Stream interface, enabling seamless integration between Xilinx FFT IP cores and a custom peak detection accelerator without intermediate memory storage. Unlike conventional radar systems that construct a two-dimensional Range–Doppler map followed by explicit scanning, the proposed approach performs detection on a linearized data stream. This eliminates the need for complex 2D search logic, reduces control overhead, and enables low-latency,
real-time operation suitable for practical radar deployments. Additionally, index-aware detection logic propagates range and Doppler indices alongside magnitude data, enabling direct extraction of target coordinates without post-processing. The modular AXI-Stream architecture ensures reusability, timing-closed operation, and reduced FPGA resource utilization compared to reference designs. The proposed system emphasizes FPGA-focused architectural optimization rather than algorithm-level modification, distinguishing it from
prior software-oriented or hybrid detection approaches. The complete processing chain achieves an end-to-end latency of approximately 1.1 ms for a full frame comprising 64 chirps, while sustaining a continuous input data rate exceeding 200 MSamples/s. The design was synthesized and simulated using the Xilinx Vivado design tool and implemented on a Zynq-7000-based ZC702 evaluation board, demonstrating efficient FPGA resource utilization of approximately 35% LUTs, 28% flip-flops, 42% BRAM, and 6 DSP slices. Simulation results confirm correct FFT operation, reliable buffering, and accurate peak detection across varying signal-to-noise ratios. The proposed architecture offers low latency, high throughput, and efficient hardware utilization, making it well-suited for practical real-time radar signal processing applications. Overall, the proposed FPGA-based solution demonstrates low latency, efficient resource usage, and reliable real-time performance, making it suitable for practical Frequency Modulated Continuous Wave (FMCW)-RADAR signal processing applications.