Low-Power FPGA Implementation of an 8-Bit Quantized MLP Neural Network for Real-Time Vehicular Prediction
DOI:
https://doi.org/10.31838/jvcs/08.01.09Keywords:
FPGA Architecture; VHDL Implementation; Quantized Neural Networks; Edge AI Hardware; Low-Power Hardware Design; Vehicular Prediction SystemsAbstract
Real-time vehicular monitoring systems increasingly rely on predictive analytics to improve transportation safety and efficiency. However, software-based ML on microcontrollers faces limitations such as high latency and power consumption. This work proposes a low-power hardware implementation of a quantized multi-layer perceptron for vehicle prediction on an FPGA for vehicle monitoring.
The proposed design combines GPS data collection, preprocessing, neural network prediction, and GSM transmission on a single VHDL-based embedded system. An 8-bit fixed-point quantization and pipelined MADD network are used to achieve high parallelization on an FPGA. Temporal GPS data analysis is performed to predict short-term vehicle trajectory and driving behavior.
The proposed design has a latency of ~2-3 ms and a power consumption of ~640 mW on an Artix-7 FPGA. The logic and DSP resources are efficiently utilized for this implementation. The proposed design achieves a position error of less than three meters for a three-second horizon for vehicle trajectory prediction.
Hardware acceleration for neural network inference on an FPGA can be a scalable and power-efficient solution for real-time vehicle monitoring and prediction.



