Full-Swing Gate Diffusion Input Based 32-Bit Arithmetic and Logic Unit: Design, Implementation, and Comparative Analysis

Rekha P; Smitha Gayathri D; Yasha Jyothi M. Shirur; Shamanth K.S; Kumar Puttaswamy Gowda; Bindu S

doi:10.31838/jvcs/08.01.07

Authors

Rekha P Department of Electronics and Communication Engineering, B. N. M. Institute of Technology, Bengaluru, Karnataka, India https://orcid.org/0000-0002-4296-5658
Smitha Gayathri D Department of Electronics and Communication Engineering, B. N. M. Institute of Technology, Bengaluru, Karnataka, India https://orcid.org/0000-0002-8618-7966
Yasha Jyothi M. Shirur Department of Electronics and Communication Engineering, B. N. M. Institute of Technology, Bengaluru, Karnataka, India https://orcid.org/0000-0001-8966-1312
Shamanth K.S Department of Electronics and Communication Engineering, B. N. M. Institute of Technology, Bengaluru, Karnataka, India https://orcid.org/0009-0009-9324-2749
Kumar Puttaswamy Gowda Department of Electronics and Communication Engineering, Dayananda Sagar College of Engineering, Bengaluru, Karnataka, India https://orcid.org/0000-0001-5717-232X
Bindu S Department of Electronics and Communication Engineering, B. N. M. Institute of Technology, Bengaluru, Karnataka, India https://orcid.org/0000-0003-1019-0357

DOI:

https://doi.org/10.31838/jvcs/08.01.07

Keywords:

Full-Swing Gate Diffusion Input (FS-GDI), Arithmetic Logic Unit (ALU), Brent–Kung Adder (BKA), Complementary Metal-Oxide- Semiconductor (CMOS)

Abstract

This paper presents the design and implementation of a 32-bit arithmetic logic unit (ALU) using the full-swing gate diffusion input (FS-GDI) technique for low-power and area-efficient digital systems. The ALU performs various arithmetic, logical, and shift operations, and
adopts a modular approach by building 1-bit FS-GDI cell and scaling to 32 bits with a Brent– Kung parallel prefix adder in the arithmetic path to balance speed and hardware complexity. Comparative implementations of the same ALU were produced in CMOS, gate diffusion input (GDI), modified-gate diffusion input (M-GDI), and FS-GDI using 45nm technology for a fair assessment. Simulation results show that the FS-GDI design achieves large reductions in power and area: a 98.42% reduction in static power, 47.64% reduction in dynamic power, 74.76% reduction in average power, 62.79% reduction in transistor count, and 70.91% reduction in power delay product (PDP), with only a minor 14.7% increase in propagation delay versus a CMOS baseline, with overall PDP improvement and acceptable timing tradeoffs. The paper also analyzes alternate adder choices, and motivates the choice of Brent–Kung for the final design. Results validate that FS-GDI provides an effective trade-off for lowpower, full-swing logic in high bit-width ALUs.