A Hardware-Efficient LUT Optimized Fault-Tolerant Reversible 64-bit Arithmetic Processor with Self-Error Correction
DOI:
https://doi.org/10.31838/jvcs/08.01.08Keywords:
Reversible Logic, Fault-tolerant Processor, Error correction Codes, Parity Checking, Hamming Code, Arithmetic Processor, Low-Power VLSI Design, FPGA Implementation, Energy-Efficient Computing, Reliable Processor Architecture.Abstract
The increasing demand for reliable and energy-efficient computing in safety and critical applications such as aerospace systems, embedded control systems and intelligent computing platforms requires processor architecture that simultaneously achieves low power consumption, high performance and robust fault tolerance. From this environment, transient and permanent errors are caused by radiation effects, voltage fluctuation, noise and timing violation, and it can significantly degrade computational accuracy and system reliability, especially in wide data path arithmetic operations. This research addresses the problem of designing an energy-efficient and fault-resilient arithmetic processor that maintains reliable operations without incurring excessive hardware overhead. To meet this objective, a self-error correction of fault tolerant 64-bit arithmetic processor architecture is proposed with reversible logic, in which parity-based error detection and Hamming code-based error correction are systematically integrated across the processor data path. The proposed design employs reversible majority-based arithmetic units, which extends error protection beyond the arithmetic core operations to include registers, branch related arithmetic and logic operation and memory interface, and ensures functional completeness for general- purpose computation. This work proposed the novelty architecture lies in the unified integration of reversible logic with a processor with wide forward error correction, enabling reliable single-bit error correction while preserving low power characteristics and reducing unnecessary logic activity. The complete design is developed using Verilog HDL and synthesized on an Artix-7 FPGA using the Xilinx Vivado design suite. The experimental results demonstrate that the proposed architecture achieves a notable reduction in LUT utilization and power consumption and significantly improves fault tolerance.



