A Hardware-Efficient Pipelined Parallel Architecture for Low-Power Trivium Cipher in Internet of Things and Embedded Applications

Praveen Kumar M S; Shailaja K; Shashidhara H R; Sudeendra Kumar K

doi:10.31838/jvcs/08.01.10

Authors

Praveen Kumar M S Department of Electronics and Communication Engineering, JSS Science and Technology University, Mysuru 570006, Karnataka, India. https://orcid.org/0000-0001-8016-5806
Shailaja K Department of Electronics and Communication Engineering, JSS Science and Technology University, Mysuru 570006, Karnataka, India. https://orcid.org/0000-0002-2443-9742
Shashidhara H R Department of Electronics and Communication Engineering, The National Institute of Engineering, Mysuru 570008, Karnataka, India. https://orcid.org/0000-0001-7973-8152
Sudeendra Kumar K Department of Electronics and Communication Engineering, PES University, Bengaluru 560085, Karnataka, India. https://orcid.org/0000-0003-2513-8519

DOI:

https://doi.org/10.31838/jvcs/08.01.10

Keywords:

Internet of Things (IoT), Lightweight Cryptography, Stream Cipher, Trivium, FPGA Implementation, Hardware Efficiency, Pipelined Architecture

Abstract

Embedded devices and Internet of Things (IoT) have increased the need for lightweight cryptographic techniques that offer high security, are energy-efficient, and perform well. Trivium is a stream cipher that is a part of eSTREAM and can be easily implemented in
hardware, but most implementations have difficulties in achieving standard measures of efficiency. In this paper, we have suggested a hardware-efficient Trivium architecture that utilizes pipelining on top of parallelism to generate keystreams for each stage of the
Trivium pipeline. Clock gating, resource sharing, and bit-slice designs have been employed to minimize power consumption in the architecture and also the area consumed. A Xilinx Artix-7 FPGA implementation of the architecture has reached throughput up to 192Mb/s; it is 36 percent power efficient and 121 area efficient than previous state-of-the-art work. The architecture suggested offers a scalable design specific to the resource-constrained IoT and embedded applications that are cost-efficient and have low energy needs.