Design of 45nm CMOS Front-End LNA for RF Receiver

Abstract

This study explains the design and analysis of a CMOS RF receiver front-end low-noise amplifier (LNA) at 45 nm, intended for wireless communication at approximately 3.4 GHz. This proposed architecture uses a cascaded inductive-degeneration topology, enabling balanced optimization of gain, noise figure, impedance matching, and power consumption. This contrasts with traditional single-stage CMOS RF front-end LNAs, which amplify through
a single stage, creating load and, worse still, reverse isolation. A cascaded configuration allocates amplification between stages, eliminates loading effects, and enhances reverse isolation, but at the expense of a lower noise contribution. The networks of input and output matching are designed to ensure that return losses do not exceed the −10 dB threshold, thereby guaranteeing stable operation within the industry target frequency range. Simulations show a forward gain (S21) of 32.6 dB, a noise figure of 0.96 dB, an input return loss of −11.6 dB, and a power consumption of 9.8 mW with a 1 V supply. A detailed comparative analysis of architectural and performance variations between two closely related CMOS RF receiver front-end designs is presented, demonstrating improved gain-to-power efficiency due to topology refinement. Additionally, process-voltage-temperature (PVT) testing is conducted to assess robustness under realistic operating conditions, ensuring consistent RF performance across process corners and environments. The findings show that the design under consideration offers an integration-based RF front-end suitable for broadband receiver applications.